module asyncfifo_256d_96w_wrapper #(
    parameter                           DATA_WIDTH = 96 ,
    parameter                           ADDR_WIDTH = 8
)(
    input                               wr_clk ,
    input                               rd_clk ,
    input                               rst ,
    input   [11:0]                      ram_dp_cfg_register,

    input   [DATA_WIDTH-1:0]            din ,
    input                               wr_en ,
    output                              full ,

    input                               rd_en ,
    output  [DATA_WIDTH-1:0]            dout ,
    output                              empty
) ;

    localparam ADDR_DEPTH = (1<<ADDR_WIDTH) ; //the width of address

    wire ram_we_n ;
    wire [ADDR_WIDTH-1:0] wr_addr ;
    wire [ADDR_WIDTH-1:0] rd_addr ;

    DW_fifoctl_s2_sf #(
        .depth(ADDR_DEPTH), 
        .push_ae_lvl(2),
        .push_af_lvl(ADDR_DEPTH-2),
        .pop_ae_lvl(2),
        .pop_af_lvl(ADDR_DEPTH-2),
        .err_mode(0), 
        .rst_mode(0),
        .push_sync(2),
        .pop_sync(2),
        .tst_mode(0)
    ) fifo_conctroller (
        .clk_push       (wr_clk) ,
        .clk_pop        (rd_clk) ,
        .rst_n          (~rst) ,

        .push_req_n     (~wr_en) , // FIFO push request
        .pop_req_n      (~rd_en) , // FIFO pop request

        .we_n           (ram_we_n) ,
        .push_empty     () ,
        .push_ae        () ,
        .push_hf        () ,
        .push_af        () ,
        .push_full      (full) ,
        .push_error     () ,

        .pop_empty      (empty) ,
        .pop_ae         () ,
        .pop_hf         () ,
        .pop_af         () ,
        .pop_full       () ,
        .pop_error      () ,

        .wr_addr        (wr_addr) ,
        .rd_addr        (rd_addr) ,
        .push_word_count() ,
        .pop_word_count () ,

        .test           (1'b0)
    ) ;

    ram_dp_256d_96w_wrapper inst_ram_dp_256d_96w_wrapper (
        .clka                   (wr_clk),
        .clkb                   (rd_clk),
        .ram_dp_cfg_register    (ram_dp_cfg_register),//12'b111_11_0_111_11_0
        //we write enable,write,active high
        .wea_n                  (ram_we_n),
        .addra                  (wr_addr),
        .dina                   (din),
        .douta                  (),

        .web_n                  (1'b1),
        .addrb                  (rd_addr),
        .dinb                   (96'b0),
        .doutb                  (dout)
    ) ;

endmodule
